Generally, electronic components may comprise several integrated circuits formed within separate chips, which are associated inside of a same package. It is necessary to form electric connections between the different tracks of the chips which need to be interconnected, as well as between the chips and the different electric tracks which come out of the package.
A solution used is to create, inside of the chip substrate layer, through interconnection vias which are formed of a conductive material, such as copper or the like.
On one side, the vias are connected to the tracks of the internal functional areas of the integrated circuit. At their other end, the vias emerge on one of the chip surfaces. These vias may be present on the upper surface side of the chip, or “front” side, that is, on the side where the substrate comprises active areas where transistors or the like are implanted. Frequently, however, these vias emerge on the opposite surface, or “back side” of the chip.
It is also possible to form connection areas on the front surface side of the chip, by forming connection areas connected to one of the metallization levels, generally the upper metallization level, formed in the insulating layer (or “back-end” layer) which covers the substrate. This insulating layer comprising metallization levels should not be mistaken for the passivation layer separating the metallization levels and the metal areas forming contact pads from the conducting layers forming a redistribution line (RDL), which are sometimes placed on top of the “back-end” layer.
Protruding areas are created on one and/or the other of the chip surfaces. They are arranged to be, on the one hand, connected to the interconnection vias or to the metallization level and, on the other hand, to be able to be soldered to the adjacent chips or to the package.
A known embodiment comprises using, as protruding areas, metal balls or spheres, generally called bumps, which are deposited on the front and/or back sides of the chip, at the level of the appropriate areas, and which will come into contact with the connections of the adjacent chip.
The bump technique has been progressively replaced with a so-called interconnection pillar technique, to increase the density of connection points. Indeed, bumps have a spherical geometry, whereby their bulk compared with the effective contact area crossed by the current is not optimal.
Conversely, interconnection pillars have a cylindrical geometry, which makes it possible to implant a larger number thereof per surface area unit.
Such interconnection pillars are generally made of copper. They are formed by electrodeposition from seed layers deposited in appropriate areas of the surface of the involved chip.